View DS1123LE-100_9054683.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the ds1123l is an 8-bit programmable timing elementsimilar in function to the ds1023, but operating at 3.3v. like the ds1023, the ds1123l can delay signals up to a full period or more when used as a delay line, and an on-chip reference delay can be used to offset the inher- ent ?tep-zero?delay. this allows the ds1123l to shift a clock signal over the full 0 to 360 phase range. in addition to functioning as a delay line, it can be config- ured as a free-running oscillator or an externally trig- gered monostable vibrator. applications telecommunicationsdigital test equipment digital video projection signal generators and analyzers features ? step sizes of 0.25ns, 0.5ns, 1ns, 2ns ? on-chip reference delay ? configurable as a delay line, monostable vibrator, or free-running oscillator ? can delay signals by a full period or more ? guaranteed monotonicity ? parallel and 3-wire serial programming interface ? single 3.3v power supply ? 16-pin tssop ds1123l 3.3v, 8-bit, programmable timing element _____________________________________________ maxim integrated products 1 1514 13 12 11 10 9 2 16 1 34 56 7 8 out/outp/s p7 p6 p2/d p1/clk p0/q le v cc in top view ms p5 ref/pwm gnd p4 p3 ds1123l pin configuration ds1123l system clock micro- processor 4 3-wire interface in q/p0 clk/p1 d/p2 p3p4 le p5 ms p6 p7 p/s out/out v cc gnd ref/pwm 3.3v variable delay/phase output reference output (optional) typical operating circuit ordering information rev 2; 8/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package (150-mil) step size/ no. of steps ds1123le-25 0? to +70? 16 tssop 0.25/256 ds1123le-50 0? to +70? 16 tssop 0.5/256 DS1123LE-100 0? to +70? 16 tssop 1/256 ds1123le-200 0? to +70? 16 tssop 2/256 downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element 2 __________________________________________________ ____________________ absolute maximum ratings recommended dc operating conditions (t a = 0? to +70?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc pin relative to ground .....-0.5v to +6.0v *voltage range on in, le, q/p0, clk/p1, d/p2, p3, p4, p5, ms, p6, p7, and p /s relative to ground ..........-0.5v to v cc + 0.5v operating temperature range...............................0 c to +70 c storage temperature range .............................-55 c to +125 c short-circuit output current .....................................50ma for 1s soldering temperature .......................................see ipc/jedec j-std-020a specification *not to exceed +6.0v parameter symbol conditions min typ max units supply voltage v cc (note 1) +3.0 +3.6 v input logic 1 v ih (note 2) 0.7 x v cc v cc + 0.3 v input logic 0 v il -0.3 +0.3 x v cc v dc electrical characteristics (v cc = +3.0 to 3.6v, t a = 0? to +70?.) parameter symbol conditions min typ max units active and standby current i cc 16 30 ma high-level output current i oh v cc = min, v oh = 2.3v -1.0 ma q output, v cc = min, v ol = 0.5v 4.0 low-level output current i ol all other outputs, v cc = min, v ol = 0.5v 8.0 ma input leakage i l -1.0 +1.0 ? downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element ___________________________________________________ __________________ 3 ac electrical characteristics (all speed options) (v cc = +3.0v to 3.6v, t a = 0? to +70?.) parameter symbol conditions min typ max units serial clock frequency f clk 10 mhz input pulse width (le, clk) t w 50 ns data setup to clock t dsc 30 ns data hold from clock t dhc 0n s data setup to enable t dse 30 ns data hold to enable t dhe 0n s enable setup to clock t es 0n s enable hold from clock t eh 30 ns le to q valid t eqv 50 ns le to q high-z t eqz 05 0 n s clk to q valid t cqv 50 ns clk to q invalid t cqx 0n s parallel input to delay valid t pdv 500 ns parallel input to delay invalid t pdx 0n s le to delay valid t edv 500 ns le to delay invalid t edx 0n s power-up time t pu 100 ms downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element 4 __________________________________________________ ____________________ ac electrical characteristics (ds1123l-25) (v cc = +3.0v to 3.6v, t a = 0? to +70?.) parameter symbol conditions min typ max units reference delay t ref (notes 3, 4) 18 22 ns delay step size t step t a = +25? 0 0.25 1.75 ns step-zero delay with respectto in t d0 (notes 4, 5) 16.5 22 ns step-zero delay with respectto ref t d0ref (notes 6, 7) -2.5 -1.5 0 ns maximum delay with respectto in t dmax (notes 4, 8) 80 ns delay with respect to ref t dref position fo (notes 7, 9) 60 ns delay with respect to reftolerance v cc = 3.3v, t a = +25? (notes 7, 9) -0.75 +0.75 % voltage delay variation (notes 7, 9) -1 +1 % temperature delay variation v cc = 3.3v (notes 7, 9) -2.5 +2.5 % integral nonlinearity (deviationfrom straight line) t err (note 10) -2 0 +2 ns out delta delay t inv0 (note 11) 0 1 2.5 ns in high to pwm high t pwm0 (notes 4, 12) 16.5 22 ns minimum pwm output pulsewidth t pwm (note 13) 5 ns minimum input pulse width t wi (note 14) 40 ns minimum input period (note 15) 80 ns input rise and fall times t r , t f (note 16) 0 1 ? ? t t dref dref ? t t dv dref ? t t dt dref downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element ___________________________________________________ __________________ 5 ac electrical characteristics (ds1123l-50) (v cc = +3.0v to 3.6v, t a = 0? to +70?.) parameter symbol conditions min typ max units reference delay t ref (notes 3, 4) 18 22 ns delay step size t step t a = +25? 0 0.5 1.75 ns step-zero delay with respectto in t d0 (notes 4, 5) 16.5 22 ns step-zero delay with respectto ref t d0ref (notes 6, 7) -2.5 -1.5 0 ns maximum delay with respectto in t dmax (notes 4, 8) 144 ns delay with respect to ref t dref position ff (notes 7, 9) 127.5 ns delay with respect to reftolerance v cc = 3.3v, t a = +25? (notes 7, 9) -0.75 +0.75 % voltage delay variation (notes 7, 9) -0.75 +0.75 % temperature delay variation v cc = 3.3v (notes 7, 9) -2.5 +2.5 % integral nonlinearity (deviationfrom straight line) t err (note 10) -2 0 +2 ns out delta delay t inv0 (note 11) 0 1 2.5 ns in high to pwm high t pwm0 (notes 4, 12) 16.5 22 ns minimum pwm output pulsewidth t pwm (note 13) 5 ns minimum input pulse width t wi (note 14) 40 ns minimum input period (note 15) 80 ns input rise and fall times t r , t f (note 16) 0 1 ? ? t t dref dref ? t t dv dref ? t t dt dref downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element 6 __________________________________________________ ____________________ ac electrical characteristics (ds1123l-100) (v cc = +3.0v to 3.6v, t a = 0? to +70?.) parameter symbol conditions min typ max units reference delay t ref (notes 3, 4) 18 22 ns delay step size t step t a = +25? 0 1 2.25 ns step-zero delay with respectto in t d0 (notes 4, 5) 16.5 22 ns step-zero delay with respectto ref t d0ref (notes 6, 7) -2.5 -1.5 0 ns maximum delay with respectto in t dmax (notes 4, 8) 272 ns delay with respect to ref t dref position ff (notes 7, 9) 255 ns delay with respect to reftolerance v cc = 3.3v, t a = +25? (notes 7, 9) -0.75 +0.75 % voltage delay variation (notes 7, 9) -0.5 +0.5 % temperature delay variation v cc = 3.3v (notes 7, 9) -2.5 +2.5 % integral nonlinearity (deviationfrom straight line) t err (note 10) -4 0 +4 ns out delta delay t inv0 (note 11) 0 1 2.5 ns in high to pwm high t pwm0 (notes 4, 12) 16.5 22 ns minimum pwm output pulsewidth t pwm (note 13) 5 ns minimum input pulse width t wi (note 14) 40 ns minimum input period (note 15) 80 ns input rise and fall times t r , t f (note 16) 0 1 ? note 1: all voltages are referenced to ground. note 2: if in is high during power-up, the output remains low until in is toggled low and back high again. note 3: the reference delay is closely matched to the step-zero delay to allow relative timings down to zero or less. note 4: measured from rising edge of the input to the rising edge of the output (t dr ). note 5: delay from input to output with a programmed delay value of zero. note 6: this is the relative delay between ref and out. the device is designed such that when programmed to zero delay theout output always appears before the ref output. this parameter is numerically equal to t d0 - t ref (see figure 8). note 7: from rising edge to rising edge. note 8: this is the actual measured delay from in to out. this parameter exhibits greater temperature variation than the relativedelay parameter. note 9: this is the actual measured delay with respect to the ref output. this parameter more closely reflects the programmeddelay value than the absolute delay parameter (see figure 8). typical delay shift due to aging is within ?.85%. aging stressing includes level 1 moisture reflow preconditioning (24hr +125? bake, 168hr +85?/85%rh moisture soak, and three solder reflow passes +260? +0?/-5? peak) followed by 1000hr (max) v cc biased +125? op/l, 1000hr unbi- ased +150? bake, and 1000 temperature cycles at -55? to +125?. ? t t dref dref ? t t dv dref ? t t dt dref downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element ___________________________________________________ __________________ 7 ac electrical characteristics (ds1123l-200) (v cc = +3.0v to 3.6v, t a = 0? to +70?.) parameter symbol conditions min typ max units reference delay t ref (notes 3, 4) 18 22 ns delay step size t step t a = +25? 1.0 2 3.0 ns step-zero delay with respectto in t d0 (notes 4, 5) 16.5 22 ns step-zero delay with respectto ref t d0ref (notes 6, 7) -2.5 -1.5 0 ns maximum delay with respectto in t dmax (notes 4, 8) 527 ns delay with respect to ref t dref position ff (notes 7, 9) 510 ns delay with respect to reftolerance v cc = 3.3v, t a = +25? (notes 7, 9) -0.75 +0.75 % voltage delay variation (notes 7, 9) -0.5 +0.5 % temperature delay variation v cc = 3.3v -2.5 +2.5 % integral nonlinearity (deviationfrom straight line) t err (note 10) -5 0 +5 ns out delta delay t inv0 (note 11) 0 1 2.5 ns in high to pwm high t pwm0 (notes 4, 12) 16.5 22 ns minimum pwm output pulsewidth t pwm (note 13) 5 ns minimum input pulse width t wi (note 14) 40 ns minimum input period (note 15) 80 ns input rise and fall times t r , t f (note 16) 0 1 s note 10: see the integral nonlinearity section and figure 9. note 11: change in delay value when the inverted output is selected instead of the normal, noninverting output. note 12: in pwm mode, the delay between the rising edge of the input and the rising edge of the output. note 13: the minimum value for which the monostable-vibrator pulse width should be programmed. narrower pulse widths can beprogrammed, but output levels may be impaired and ultimately no output pulse is produced. note 14: this is the minimum allowable interval between transitions on the input to assure accurate device operation. this parame-ter may be violated, but timing accuracy may be impaired and ultimately very narrow pulse widths result in no output from the device. note 15: this parameter applies to normal delay mode only. when a 50% duty cycle input clock is used this defines the highestusable clock frequency. when asymmetrical clock inputs are used, the maximum usable clock frequency must be reduced to conform to the minimum input pulse-width requirement. in pwm mode, the minimum input period is equal to the step-zero delay and the programmed delay (t do +t d ). note 16: faster rise and fall times give the greatest accuracy in measured delay. slow edges (outside the specification maximum)can result in erratic operations. ? t t dref dref ? t t dv dref ? t t dt dref downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element 8 __________________________________________________ ____________________ detailed description the ds1123l is an 8-bit programmable delay line thatcan be adjusted between 256 different delay intervals. because of the design (see figure 1) of the ds1123l, it is possible to delay a signal by a whole period or more, which allows the phase of the signal to be adjusted up to a full 360? programming may be done using either an 8-bit parallel interface or a 3-wire serial interface. using the 3-wire interface, it is possible to cascade multiple devices together for systems requiring multiple pro- grammable delays without using additional i/o resources. the ds1123l also features a reference delay that is approximately equal to the step-zero delay, which can be used to realize small relative delays. additionally, the ds1123l can function as a monostable vibrator or an adjustable frequency oscillator. device operation this section details how to program the ds1123l usingboth the parallel and serial interfaces, using the refer- ence delay, and how to configure the chip to function as a monostable vibrator or adjustable frequency oscillator. using the parallel programming interface to enable the ds1123l? parallel interface, p /s must be connected to ground. this allows the data on the paral-lel inputs (p0 to p7) to pass through the latch, which are transparent when latch enable (le) is at a high input level. when le is at a low level, the data is latched until le is returned to a high state. if the parallel inputs are going to be used to hardwire a delay, le must be connected to v cc to allow the setting to take ds1123l reference delay programmable delay in p/s le p3-p7 p0/q p1/clk p2/d 5 8 8 8-bit latch 8-bit input register output mode control out/out ref/pwm pin name function 1i n input signal to be delayed, pwmtrigger 2 le input-latch enable 3 p0/q input p0 (parallel mode)/serial data output (serial mode) 4 p1/clk input p1 (parallel mode)/serial clock (serial mode) 5 p2/d input p2 (parallel mode)/serial data input (serial mode) 6 p3 input p3 7 p4 input p4 8 gnd ground 9 ref/pwm reference output/pwm output 10 p5 input p5 11 ms input mode selectms = 0 for delay function, ms = 1 for oscillator or pwm 12 p6 input p6 13 p7 input p7 14 p /s parallel/serial programming select 15 out/ out delay output or inverted output 16 v cc power supply (3.3v) pin description functional diagram t d t d t d t d out in 256 line decoder 8-bit latch value 256 control lines ref 255 unit delay cells figure 1. ds1123l conceptual design downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element ___________________________________________________ __________________ 9 effect on power-up. the most flexibility when using par-allel mode occurs when the delay is being controlled by a microprocessor. there are two common parallel interface implementa- tions used to control the ds1123l using a microproces- sor (see figure 2). le can be used to latch the data from the microprocessor, which allows the data bus to be shared with other peripherals, or le can be tied high, which causes the ds1123l to adjust its delayimmediately following a change to the parallel inputs. for each configuration, a settling time (t edv or t pdv ) is required after an adjustment is made before the inputsignal is accurately delayed according to the new set- ting. figures 3 and 4 show the timing required for these implementations. using the serial programming interface the 3-wire serial interface is enabled by connecting p /s to v cc . serial mode operates similar to a shift register. when le is set at a high logic level, it enables the reg-ister and clk clocks the data, d, into the register one bit at a time starting with the most significant bit. after all 8 bits are shifted into the ds1123l, le is pulled low to end the data transfer and activate the new value. a settling time (t edv ) is required after le is pulled low before the signal delay meets its specified accuracy. atiming diagram for the serial interface is shown in figure 6. the 3-wire interface also has an output (q) that can be used to cascade multiple 3-wire devices, and it can be used to read the current value of the devices on the bus. le p0-p7 p/s 8 microprocessor additional peripheral additional peripheral a) sharing the parallel interface with additional peripherals microprocessor 8 b) a parallel interface dedicated to a ds1123l v cc ds1123l le p0-p7 p/s ds1123l figure 2. parallel interface options for ds1123l previous value parallel inputs p0?7 delay time new value new value previous value t pdx t pdv figure 3. nonlatched parallel timing diagram enable (le) previous value new value new value t ew t dse t edx t edv t dhe parallel inputs po?7 delay time figure 4. latched parallel timing diagram downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element 10 _________________________________________________ ____________________ to read the current values stored by the 3-wiredevice(s), the latch must be enabled and the value of q must be read and then written back to d before the register is clocked. this causes the current value of the register to be written back into the ds1123l as it is being read. this can be accomplished in a couple of different ways. if the microprocessor has an i/o pin that is high impedance when set as an input, a feedback resistor (generally between 1k and 10k ) can be used to write the data on q back to d as the value isread (see figure 5a). if the microprocessor has an internal pullup on its i/o pins, or only offers separate input and output pins, the value in the register can still be read. the circuit shown in figure 5b allows the qvalues to read by the microprocessor, which must write the q value to d before it can clock the bus to read the next bit. if the q values are read without writing them to d (with the pullup or otherwise), the read is destructive. a destructive read cycle likely results in an undesirable change in the delay setting. figure 5c shows how to cascade multiple ds1123l? onto the same 3-wire bus. one important detail of writ- ing software for cascaded 3-wire devices is that all the devices on the bus must be written to or read from dur- ing each read or write cycle. attempting to write to only the first device (u1) would cause the data stored in u1 microprocessor outputoutput i/o pin leclk dq r fb microprocessor outputoutput output input a) using a feedback resistor with an i/o pin for reading the ds1123l b) using a separate input pin to read the ds1123l microprocessor leclk dq leclk dq leclk dq outputoutput i/o pin r fb c) cascading multiple ds1123l's on a 3-wire bus v cc v cc v cc v cc v cc leclk dq p/s p/s p/s p/s p/s ds1123l ds1123l u1 u2 u3 ds1123l ds1123l ds1123l figure 5. using the serial interface downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element ___________________________________________________ _________________ 11 to be shifted to u2, u2? data would be shifted to u3, etc.as shown, the microprocessor would have to shift 24 bits during each read or write cycle to avoid inadvertently changing the settings in any of the 3-wire devices. also note that the feedback resistor or a separate input (not shown) can still be used to read the 3-wire device set- tings when multiple devices are cascaded. configuring the ds1123l as a delay line to use the ds1123l as a delay line, the ms pin mustbe tied to ground. when used as a delay line, the inter- nal architecture of the ds1123l allows the output delay time to be considerably longer than the input pulse width (see ac specifications). this feature is useful in many applications, in particular in clock phase control, where delays up to and beyond one full clock period can be achieved. table 1 lists some of the delay char- acteristics of the different speed options available for the ds1123l device. using the reference delay all delay lines have an inherent step-zero delaybetween in and out (t d0 ) due to the propagation delay through the input and output buffers. to simplifysystem design, a reference delay has been included on the ds1123l that can be used to compensate for thestep-zero delay. the reference output allows the ds1123l to be used to generate small differential delays that cannot be generated when the out delay is referenced to the input. the step-zero out delay is always approximately 1ns faster than the ref delay (see figure 8). this allows the ds1123l to generate a nondelayed output with respect to the reference output. in addition, the reference output driver is sized similarly to the out output driver, both outputs act similarly over temperature, and they are both triggered at the same time regardless of the exact input threshold. these fea- tures make the output delay with respect to the refer- ence act more ideally because both of these outputs are skewed approximately the same amount due to these phenomena. integral nonlinearity integral nonlinearity (inl) is defined as the deviation froma straight line response drawn between the measured step-zero delay and the measured step 255 delay with respect to the reference output. inl measured with respect to in is not specified, but should be slightly high- er than when measured with respect to the reference out- put. this is because measurements taken with respect to t ew t cw t es t eh t dsc t egv t cqx t cqv t edz t eqz t edx t dhc t cw previous value new value new bit 7 new bit 0 new bit 6 old bit 7 old bit 6 old bit 0 enable (le) clock (clk) serial input (d) serial input (q) delay time figure 6. serial interface timing diagram downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element 12 _________________________________________________ ____________________ in do not benefit from the ref output? tendency to trackout over temperature and voltage. figure 9 shows inl? effect on delay performance graphically. configuring the ds1123l as a monostable vibrator or pwm to configure the ds1123l as a monostable vibrator, setms = 1. this causes the reference output (pwm) to be set high between t ref and t d when it is triggered by the input. after time period t d has elapsed, the output returns low, and the monostable vibrator can be retrig-gered. see figure 10 for the timing of the out and pwm signals. when ms = 1 and the ds1123l is trig-gered by an external free-running oscillator, reference output becomes a pulse-width modulator (pwm). when using the ds1123l as a pwm, the free-running oscillator should not be generated by connecting out to the input. this causes the pwm period to change in addition to theduty cycle as different values are programmed, which is most likely not the desired functionality. the minimum pulse width that can be practically gener-ated is approximately 5ns. this is because a 5ns pulse is approximately the shortest pulse that can be pro- duced with the ds1123l? output driver. the mono- stable vibrator cannot be retriggered, so subsequent triggering pulses into in should not be present until after the output has returned low. configuring the ds1123l as an oscillator to configure the ds1123l as an adjustable oscillator,set ms = 1 and externally connect out to in. setting ms = 1 by itself inverts the input signal in addition todelaying it (see figure 10). connecting out to the input then causes the circuit to oscillate with the periodbeing twice the programmed delay. table 2 shows the oscillator frequency ranges that the different speed grades of ds1123ls provide. ref in out ref in out ds1123l t wi t ref t d0 t dmax t dmax figure 7. reference delay timing, ms = 0 delay t dmax t ref t ref0 t dref step 255 0 t d0 figure 8. delay parameters step line fit betweenmeasured max and min delay measured delay for all steps 0 64 128 192 255 inl exaggerated delay measured t dref measured t d0 t ref figure 9. integral nonlinearity downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element ___________________________________________________ _________________ 13 application information power-supply decoupling to achieve the best results when using the ds1123l,decouple the power supply with a 0.01? and a 0.1? capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possi- ble to the v cc and gnd pins of the ds1123l to mini- mize lead inductance. the ds1123l may not perform asspecified if good decoupling practices are not followed. unused inputs when using the serial- programming mode when using the serial-programming mode, the unusedparallel inputs must be connected to v cc or gnd to pre- vent them from floating and drawing excessive current. test conditions input: ambient temperature: 25? 3? supply voltage (v cc ): 3.3v 0.1v input pulse: high = 3.0v 0.1v low = 0.0v 0.1v source impedance: 50 (max) rise and fall times: 3.0ns (max) (measured between 0.6v and 2.4v) pulse width: 500ns period: 1? output: the outputs are loaded with a 74f04. delay is measured between the 1.5v level of the rising orfalling edge of the input signal and the corresponding edge of the output signal. note: above conditions are for test only and do not restrict the operation of the device under other datasheet conditions. part step size (ns) max delay time and max pulse width* (ns) max integral nonlinearity (ns) max input frequency (mhz) min input pulse width (ns) ds1123l-25 0.25 63.75 ? 25 40 ds1123l-50 0.5 127.5 ? 25 40 ds1123l-100 1.0 255 ? 25 40 ds1123l-200 2.0 510 ? 25 40 table 1. ds1123l delay line/pwm ranges and tolerances * this is the maximum delay in normal mode (ms = 0) measured with respect to the reference output, and the maximum pulse width in monostable vibrator mode (ms = 1). part period change/step (ns) min oscillator frequency (mhz) max oscillator frequency* (mhz) ds1123l-25 0.5 6.6 22 ds1123l-50 1.0 3.6 22 ds1123l-100 2.0 1.9 22 ds1123l-200 4.0 0.98 22 table 2. ds1123l adjustable oscillator characteristics * maximum output frequency depends on the actual step-zero delay value. worst-case values are shown in the table. output period is equal to 2 x td, where td = delay value referenced to in. in pwm out t ref t d figure 10. output timing diagram for ms = 1 downloaded from: http:///
ds1123l 3.3v, 8-bit, programmable timing element maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . chip topology transistor count: 6057substrate connected to ground revision history pages changed at rev 2: 1, 6, 14 downloaded from: http:///

▲Up To Search▲

Price & Availability of DS1123LE-100

	To Download DS1123LE-100 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .